Kernel DMA/IOMMU & Zero-Copy Systems Architect Edit listing

### About Velaura

Velaura is building the next generation of compute platforms for Physical AI.

As AI moves beyond the datacenter into robots, autonomous mobile systems, drones, and other embodied systems, traditional compute architectures are increasingly constrained by power, memory bandwidth, latency, real-time requirements, and functional safety considerations.

Our mission is to develop the foundational compute technologies that enable intelligent systems to operate efficiently in the physical world.

We are assembling a team of exceptional architects and engineers to rethink how AI, sensing, memory, and control interact within a modern computing platform.

### Role Overview

We are looking for a senior Kernel DMA/IOMMU & Zero-Copy Systems Architect to own critical Linux kernel infrastructure for high-throughput, low-latency data movement across Velaura's AI SoC.

This role will focus on DMA, IOMMU/SMMU, cache coherency, memory allocation, dma-buf, zero-copy pipelines, and kernel/user-space memory interfaces for cameras, ISP, video, NPU, and robotics workloads. The ideal candidate is a senior individual contributor or architect-level engineer with deep Linux kernel memory-management expertise and experience making heterogeneous compute pipelines fast, reliable, and debuggable.

### Responsibilities

* Own Linux kernel memory, DMA, IOMMU/SMMU, cache-coherency, and dma-buf architecture for the SoC.
* Define zero-copy buffer-sharing strategies across camera, ISP, video, NPU, display, and user-space runtime components.
* Work with platform, multimedia, accelerator driver, runtime, and compiler teams to design robust memory allocation and buffer lifetime models.
* Debug memory corruption, DMA mapping, IOMMU faults, coherency bugs, cache-maintenance problems, and memory-bandwidth bottlenecks.
* Define kernel/user-space memory APIs and constraints for accelerator runtime, camera pipelines, and SDK components.
* Partner with hardware architects on coherency, SMMU topology, reserved memory, carveouts, address translation, QoS, and memory bandwidth behavior.
* Drive integration of dma-buf, dma-fence, scatter-gather, contiguous memory allocation, and related Linux kernel mechanisms where appropriate.
* Establish correctness and performance tests for shared memory, DMA, zero-copy paths, multi-camera workloads, and NPU ingest paths.
* Review and guide driver implementations that interact with shared memory and DMA-capable devices.
* Contribute to upstream-quality kernel designs, documentation, and hardware/software interface specifications.

### Required Qualifications

* Deep Linux kernel development experience, especially in memory management, DMA, IOMMU/SMMU, cache coherency, or driver memory interfaces.
* Strong understanding of DMA mapping APIs, scatter-gather memory, page pinning, memory allocators, reserved memory, and cache maintenance.
* Experience debugging kernel memory, IOMMU, coherency, or DMA issues on embedded or heterogeneous compute systems.
* Strong C programming skills and ability to work in complex kernel codebases.
* Familiarity with kernel tracing and debugging tools such as ftrace, perf, lockdep, KASAN, crash dumps, or equivalent.
* Ability to work across hardware architecture, kernel drivers, accelerator runtime, camera/media, and validation teams.
* Strong written communication skills for documenting constraints, APIs, and hardware/software contracts.

### Preferred Qualifications

* Experience with Linux dma-buf, dma-fence, DRM, V4L2/media, GPU, NPU, ISP, or video pipelines.
* Experience with ARM SMMU/IOMMU, non-coherent devices, memory bandwidth optimization, or real-time/low-latency systems.
* Experience designing zero-copy camera-to-accelerator or video-to-accelerator pipelines.
* Experience with AI accelerators, GPUs, robotics platforms, cameras, or multimedia SoCs.
* Experience with upstream Linux development or review.
* Familiarity with security and isolation implications of IOMMU and shared-buffer designs.

### Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance-based incentives, and equity participation, allowing team members to share in the company's long-term success. The base pay range for this role is between $200k and $500k, and your base pay will depend on your skills, qualifications, experience, and location.

In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage, paid time off, flexible work arrangements, professional development opportunities, and other benefits designed to support the well-being and growth of our team.

Velaura is committed to pay equity and transparency, and we regularly benchmark compensation to ensure we remain competitive in the market.

### Why Velaura?

This is an opportunity to help build a new class of computing architecture at a time when the industry is undergoing fundamental change.

You will work alongside experienced leaders and architects who have delivered industry-defining products across mobile, cloud, and AI platforms.

If you enjoy building hardware, tackling difficult technical challenges, and helping shape the future of Physical AI, we would love to hear from you.